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INTEGRATED CIRCUITS
DATA SHEET
SAA7112 Decoder with High-Performance Scaler (HPS) for Image Port (PELICAN)
Preliminary specification File under Integrated Circuits, IC22 1996 Jun 20
Philips Semiconductors
Preliminary specification
Decoder with High-Performance Scaler (HPS) for Image Port (PELICAN)
FEATURES The PELICAN SAA7112 is a video capture device for application at the image port of a VGA controller, with following feature highlights: Video Decoder * Six analog inputs, internal analog source selectors, (e.g. 6 x CVBS or(2 x YC and 2 x CVBS) or (1 x YC and 4 x CVBS) * Two analog preprocessing channels, including built in analog anti-alias filters * Fully programmable static gain for the main channels or Automatic Gain Control (AGC) for the selected CVBS/Y channel * Two 8 bit video CMOS Analog-to-Digital Converters (ADCs) * Automatic Clamp Control (ACC) for CVBS, Y and C * Switchable white peak control * On-chip line locked clock generation in accordance with CCIR-601 * Digital PLL for synchronization and clock generation from all standards and non-standard video sources, e.g. consumer grade VTR * Requires only one crystal (32.11 MHz) for all standards * Horizontal and vertical sync detection * Automatic detection of 50/60Hz field frequency, and automatic switching between standards PAL and NTSC * Luminance and chrominance signal processing for PAL BGHI, PAL N, PAL M, NTSC M, NTSC N, NTSC 4.43 and SECAM * User programmable luminance peaking or aperture correction * Cross-colour reduction for NTSC by chrominance combination filtering * PAL delay line for correcting PAL phase errors * Real time status information output (RTCO) * Independent Brightness Contrast Saturation (BCS) adjustment for decoder part. Video Scaler * Horizontal and vertical down-scaling and up-scaling to randomly sized windows * Horizontal and vertical scaling range: 2 (zoom) to 164 (icon); vertical zoom might be restricted * Anti-alias- and accumulating filter for horizontal scaling
SAA7112
* Vertical scaling with linear phase interpolation (6-bit phase accuracy) and accumulating filter for anti-aliasing * Horizontal phase correct up- and down-scaling for improved signal quality of scaled data, especially for compression and video phone applications, with 6-bit phase accuracy * Two independent programming sets for scaler part, to define two `ranges' per field or per frame * Field-wise switching between decoder-part and expansion port input * Brightness, contrast and saturation controls for scaled outputs. VBI-data decoder and text slicer * versatile VBI-data decoder, slicer, clock regeneration and byte synchronization; e.g. for WST, NABST, Close Caption, WSS, etc. Audio clock generation * Generation of a field locked audio master clock to support a constant number of audio clocks per video field * Generation of an audio serial and left/right (channel) clock signal. Digital I/O interfaces * Real time signal port (R-port), including continuous line locked reference clock and real time status information * Bidirectional expansion port (X-port) with half duplex functionality (D1), 8-bit YUV - output from decoder part, real time, or - input to scaler part, e.g. video from MPEG-decoder * Video image port (I-port) configurable for 8-bit (16-bit) data in master mode (own clock), or slave mode (external clock), with auxiliary timing and hand shake signals * 8-bit data Host port (H-port) for 16-bit extension of I-port * Discontinuous data streams supported * 32-word x 4 bytes FIFO register for video output data
1996 Jun 20
2
Philips Semiconductors
Preliminary specification
Decoder with High-Performance Scaler (HPS) for Image Port (PELICAN)
* 16-word x 4 bytes FIFO register for decoded VBI output data Scaled 4 : 2 : 2, 4 : 1 : 1 YUV output * Scaled 8-bit luminance only and raw data output * Decoded VBI data output. miscellaneous * Power-on control * Programming via I2C-bus, or parallel image data port (full read-back ability by an external controller) * Chip enable function (reset for the clock generator). APPLICATIONS * Desktop video * Multimedia * Digital television * Image processing * Video phone. GENERAL DESCRIPTION The PELICAN SAA7112 is a video capture device for applications at the image port of VGA controllers. The SAA7112 is a combination of a two channel analog preprocessing circuit including source-selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multistandard decoder and a SAA7140B based scaler, including variable horizontal and vertical up and down QUICK REFERENCE DATA SYMBOL VDDD VDDA Tamb digital supply voltage analog supply voltage ambient temperature PARAMETER 3.0 3.0 0 MIN. MAX. 3.6 3.6 70
SAA7112
scaling and a brightness, contrast and saturation control circuit (see Fig.1). It is a highly integrated circuit for desktop video applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL, SECAM and NTSC signals into CCIR-601 compatible colour component values. The SAA7112 accepts as analog inputs CVBS or S-video (Y-C) from TV or VCR sources, including weak and distorted signals. An Expansion port for digital video (bidirectional half duplex, D1 compatible) is also supported to connect to MPEG or video phone CODEC. At the so called image port the SAA7112 supports 8-bit (16-bit) wide output data with auxiliary reference data for interfacing to VGA controllers The target application for PELICAN is to capture and scale video images, to be provided as digital video stream through the image port of a VGA controller, for display via VGAs frame buffer, or for capture to system memory. In parallel the SAA7112 incorporates also provisions for capturing the serially coded data in the vertical blanking interval (VBI-data). Two principal functions are available: to capture raw video samples and a versatile data slicer (data recovery) unit. The SAA7112 incorporates also a field locked audio clock generation. This function ensures that there is always the same number of audio samples associated with a field, or a set of fields. This prevents the loss of synchronization between video and audio, during capture or playback. The circuit can be controlled via the I2C-bus or via its fast parallel programming mode of the image port interface (full write/read capability).
UNIT V V C
ORDERING INFORMATION TYPE NUMBER SAA7112 PACKAGE NAME LQFP100 DESCRIPTION plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm VERSION SOT407-1
1996 Jun 20
3
Philips Semiconductors
Preliminary specification
Decoder with High-Performance Scaler (HPS) for Image Port (PELICAN)
BLOCK DIAGRAMS
SAA7112
handbook, full pagewidth
XCLK LLC2 LLC RTCA RTS0 RTS1 XDQ XRH XRV XREC XTRI
XPD7 to XPD0
RT OUT
EXPANSION PORT PIN MAPPING D1 OUT D1 IN chroma of 16-bit mode from host port a
RESIN RESON CE XOUT XTALI XTAL CLOCK GENERATION AND POWER ON CONTROL
X PORT INPUT FORMATTER (SELECT)
AI11 AI12 AI21 AI22 AI23 AI24 AOUT ANALOG DUAL ADC SAA7111A BASED DIGITAL DECODER 4:2:2 OUTPUT INTERFACE
data, clock, H, V, FID and qualifier to scaler b
AMCLK
AUDIO MASTER CLOCK GENERATION
Vref
Vref data, clock, H, V, FID and qualifier to text slicer c
ALRCLK ASCLK AXMCLK
AUDIO BIT BLOCK WORD SELECT GENERATION
MGE859
Fig.1 Block diagram (continued in Fig.2).
1996 Jun 20
4
Philips Semiconductors
Preliminary specification
Decoder with High-Performance Scaler (HPS) for Image Port (PELICAN)
SAA7112
handbook, full pagewidth
HRWNF HADP HACNSD HCST HDSNSC
HPD7 to HPD0
HOST PORT PIN MAPPING chroma of 16-bit input mode a from event controller A/B REGISTER MUX CLOCK MULTIPLEXER INCLUDING TCB I2C-BUS chroma of 16-bit output mode LPB PROG PROG. PORT CONTROL PROGRAMMING REGISTER ARRAY data, clock, H, V, FID and qualifier from scaler input selector
SLEEP MODE REGISTER
b
INPUT ACQUISITION CONTROL
FIR-FILTER LUMINANCE
PRESCALING LUMINANCE 4:2:2 BCS CONTROL LINE FIFO BUFFER
VERTICAL SCALING PROCESSOR
HORIZONTAL PHASE SCALING LUMINANCE IMAGE PORT PIN MAPPING
IPD7 to IPD0
FIR FILTER CHROMINANCE
PRESCALING CHROMINANCE
LINE MEMORY 1H * 16 BIT
HORIZONTAL PHASE SCALING CHROMINANCE
IRH
IRV
EVENT CONTROLLER
OUTPUT ACQUISITION CONTROL
YUV OUTPUT FORMAT
VIDEO FIFO 32 x 32
IDQE 32 TO 8 (16) MUX
ICRQF FF IP OUT
FIFO CONTROL
ITRDY
data, clock and reference signals from text input selector c
FIFO CONTROL
ICLK 32 TO 8 (16) MUX
ITRI LPB VIDEO OUT
MGE860
GENERAL PURPOSE TEXTSLICER
TXT INTERFACE
TEXT FIFO 16 x 32
VIDEO / TEXT ARBITER
Fig.2 Block diagram (continued from Fig.1).
1996 Jun 20
5
Philips Semiconductors
Preliminary specification
Decoder with High-Performance Scaler (HPS) for Image Port (PELICAN)
PACKAGE OUTLINE LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
SAA7112
SOT407-1
c
y X 75 76 51 50 ZE A
e E HE wM bp L pin 1 index 100 1 ZD bp D HD wM B vM B 25 vM A 26 detail X A A2
Q A1 (A 3) Lp
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.5 1.3 A3 0.25 bp 0.28 0.16 c 0.18 0.12 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 Q 0.70 0.57 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 7 0o
o
16.25 16.25 15.75 15.75
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT407-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-12-19
1996 Jun 20
6
Philips Semiconductors
Preliminary specification
Decoder with High-Performance Scaler (HPS) for Image Port (PELICAN)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7112
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1996 Jun 20
7
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com/ps/ (1) ADDRESS CONTENT SOURCE July 9, 1997 SCA49
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands
657021/01/pp8 Date of release: 1996 Jun 20 Document order number: 9397 750 00923

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